1. Field of the Invention
The present invention generally relates to structures and manufacturing methods for integrated circuits including field effect transistors (FETs) and, more particularly, to high performance FETs suitable for integrated circuits formed at high integration density.
2. Description of the Prior Art
It has been recognized for some years that increased integration density in integrated circuits provides not only improvements in performance and functionality but manufacturing economy, as well. Reduced device sizes and increased numbers of devices on a single chip of a given size have driven designs operating at reduced voltages.
Specifically, one effect of reducing channel or gate length below 50 nanometers is the difficulty in turning off the transistor even in the high dose halo implant. Power dissipation is thus increased since the transistors, in effect, cannot be fully turned off.
It is known to place gates on opposing sides of a channel of an FET which results in substantial improvements in FET performance (confirmed by theoretical and experimental studies). This is possible using gate structures which partially or fully surround the conduction channel. However, these same studies have demonstrated a requirement for an extremely thin diffusion region since, for short gate lengths of interest, the gate length must be maintained about 2–4 times the diffusion thickness. That is, for gate lengths of 20–100 nanometers, the diffusion thickness forming the channel must be held to 5–50 nanometers. Several proposals have been advanced for developing such a thin silicon region.
Another complication with the placement of gates on opposite sides of the channel is that many known fabrication processes provide a gate structure which wraps around the conduction channel in a single body. Therefore the entire gate can only be driven to a single voltage even though it is desirable in some circumstances to place different voltages on opposite sides of the conduction channel. Conversely, true dual-gate transistor designs that have separated gate electrodes generally present severe difficulties in forming connections to the separated gate electrodes.
Recently, dual gate devices have been proposed which appear promising at gate dimensions below 70 nm. The performance of these devices is optimal if the two gates are self-aligned, satisfy the silicon thickness to gate dimension ratio outlined in the previous paragraph and specifically do not suffer from increased gate to junction capacitance. Additionally, it is important to have reduced source to drain resistance.
Further, the manufacture of transistors having conduction channels of sub-lithographic dimensions has been complicated and manufacturing processes have generally been complex, costly and having narrow process windows and correspondingly low yield. Not only are the conduction channel dimensions very critical to the performance of the transistor but the conduction channel generally must also be monocrystalline in order to have acceptable and reasonably uniform electrical characteristics.